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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
May 2001
FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
General Description
FM24C128 is a 128Kbit CMOS non-volatile serial EEPROM organized as 16K x 8 bit memory. This device confirms to Extended IIC 2-wire protocol that allows accessing of memory in excess of 16Kbit on an IIC bus. This serial communication protocol uses a Clock signal (SCL) and a Data signal (SDA) to synchronously clock data between a master (e.g. a microcontroller) and a slave (EEPROM). FM24C128 is designed to minimize pin count and simplify PC board layout requirements. FM24C128 offers hardware write protection where by the entire memory array can be write protected by connecting WP pin to VCC. The entire memory then becomes unalterable until the WP pin is switched to VSS. "LZ" and "L" versions of FM24C128 offer very low standby current making them suitable for low power applications. This device is offered in SO, TSSOP and DIP packages. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption.
Features
I Extended operating voltage: 2.5V to 5.5V I Up to 400 KHz clock frequency at 2.5V to 5.5V I Low power consumption -- 0.5mA active current typical -- 10A standby current typical -- 1A standby current typical (L version) -- 0.1A standby current typical (LZ version) I Schmitt trigger inputs I 64 byte page write mode I Self timed write cycle (6ms max) I Hardware Write Protection for the entire array I Endurance: up to 100K data changes I Data Retention: Greater than 40 years I Packages: 8-Pin DIP, 8-Pin SO and 8-Pin TSSOP I Temperature range -- Commercial: 0C to +70C -- Industrial (E): -40C to +85C -- Automotive (V): -40C to +125C
Block Diagram
VSS VCC WP SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR E2PROM ARRAY WRITE LOCKOUT H.V. GENERATION TIMING &CONTROL
SCL
XDEC
A2 A1 A0
WORD ADDRESS COUNTER
R/W
YDEC
CK DIN DATA REGISTER DOUT
(c) 2001 Fairchild Semiconductor Corporation FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Connection Diagram
Dual-in-Line Package (N), SO Package (MW8) and TSSOP Package (MT8)
A0 A1 A2 VSS 1 2 8 7 VCC WP SCL SDA
FM24C128
3 4 6 5
See Package Number N08E, M08D and MTC08
Pin Names
VSS SDA SCL WP VCC A0, A1, A2 Ground Serial Data I/O Serial Clock Input Write Protect Power Supply Device Address Inputs
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information FM 24 C XX F LZ E YY X Letter
Blank X Package N MW8 MT8 Blank E V Blank L LZ Blank F 128 C Interface 24 FM
Description
Tube Tape and Reel 8-pin DIP 8-pin SOIC 8-pin TSSOP 0 to 70C -40 to +85C -40 to +125C 4.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V and <1A Standby Current 100KHz 400KHz 128K with write protect CMOS IIC - 2 Wire Fairchild Non-Volatile Memory
Temp. Range
Voltage Operating Range
SCL Clock Frequency Density
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating -65C to +150C 6.5V to -0.3V +300C 2000V min.
Operating Conditions
Ambient Operating Temperature FM24C128 FM24C128E FM24C128V Positive Power Supply FM24C128 FM24C128L FM24C128LZ 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V 2.5V to 5.5V 2.5V to 5.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB ILI ILO VIL VIH VOL Active Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 2.1 mA fSCL = 400 KHz fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7
Limits Typ (Note 1)
0.5 10 0.1 0.1
Units Max
1.0 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A V V V
Low VCC (2.5V to 5 .5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB (Note 3) ILI ILO VIL VIH VOL Active Power Supply Current fSCL = 400 KHz fSCL = 100 KHz Standby Current VIN = GND or VCC VCC = 2.5V - 4.5V (L) VCC = 2.5V - 4.5V (LZ) VCC = 4.5V - 5.5V
Limits Typ (Note 1)
0.5 1 0.1 10 0.1 0.1
Units Max
1.0 10 1 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A A A V V V
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7 IOL = 2.1 mA
Capacitance TA = +25C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O CIN
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Conditions
VI/O = 0V VIN = 0V
Max
8 6
Units
pF pF
Note 1: Typical values are TA = 25C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested. Note 3: The "L" and "LZ" versions can be operated in the 2.5V to 5.5V VCC range. However the ISB values for L and LZ are applicable only when VCC is in the 2.5V to 4.5V range.
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input & Output Timing Levels Output Load VCC x 0.1 to VCC x 0.9 10 ns VCC x 0.3 to VCC x 0.7 1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC 0.1VCC 0.7VCC 0.3VCC
Read and Write Cycle Limits (Standard and Low VCC Range 2.5V - 5.5V)
Symbol
fSCL TI
Parameter
SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) SCL Low to SDA Data Out Valid Time the Bus Must Be Free before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time
100 KHz Min Max
100 100 0.3 4.7 4.0 4.7 4.0 4.7 0 250 1 300 4.7 300 6 3.5
400 KHz Min Max
400 50 0.1 1.3 0.6 1.5 0.6 0.6 0 120 0.3 300 0.6 50 6 0.9
Units
KHz ns s s s s s s ns ns s ns s ns ms
tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR
Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the FM24C128 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer "Write Cycle Timing" diagram.
Bus Timing
tF tHIGH tLOW SCL tSU:STA SDA IN tHD:DAT tSU:DAT tSU:STO tLOW tR
tHD:STA
tBUF tAA tDH
SDA OUT
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION START CONDITION
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Typical System Configuration
VCC VCC
SDA SCL Master Transmitter/ Receiver
Note:
Slave Receiver
Slave Transmitter/ Receiver
Master Transmitter
Master Transmitter/ Receiver
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k)
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Background Information (IIC Bus)
Extended IIC specification is an extension of Standard IIC specification to allow addressing of EEPROMs with more than 16Kbits of memory on an IIC bus. The difference between the two specifications is that Extended IIC specification defines two bytes of "Array Address" information while Standard IIC specification defines only one. All other aspects are identical between the two specifications. Using two bytes of Array Address and 3 address signals (A2, A1 and A0), it is now possible to address up to 4 Mbits (28 * 28 * 23 * 8 = 4 Mbits) of memory on an IIC bus. Note that due to format difference, it is not possible to have peripherals which follow Standard IIC specification (e.g. 16K bit EEPROM) and peripherals which follow Extended IIC specification (e.g. 128K bit EEPROM) on a common IIC bus. IIC bus allows synchronous bi-directional communication between a TRANSMITTER and a RECEIVER using a Clock signal (SCL) and a Data signal (SDA). Additionally there are up to three Address signals (A2, A1 and A0) which collectively serve as "chip select signal" to a device (e.g. EEPROM) on the bus. All communication on the IIC bus must be started with a valid START condition (by a MASTER), followed by transmittal (by the MASTER) of byte(s) of information (Address/Data). For every byte of information received, the addressed RECEIVER provides a valid ACKNOWLEDGE pulse to further continue the communication unless the RECEIVER intends to discontinue the communication. Depending on the direction of transfer (Write or Read), the RECEIVER can be a SLAVE or the MASTER. A typical IIC communication concludes with a STOP condition (by the MASTER). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]--[DEVICE/PAGE BLOCK SELECTION]--[R/W BIT]--[ARRAY ADDRESS#1]--[ARRAY ADDRESS#0]
Device Type
IIC bus is designed to support a variety of devices such as RAMs, EPROMs etc., along with EEPROMS. Hence to properly identify various devices on the IIC bus, a 4-bit "Device Type" identifier string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC device on the bus internally compares this 4-bit string to its own "Device Type" string to ensure proper device selection.
Device/Page Block Selection
When multiple devices of the same type (e.g. multiple EEPROMS) are present on the IIC bus, then the A2, A1 and A0 address information bits are used in device selection. Every IIC device on the bus internally compares this 3-bit string to its own physical configuration (A2, A1 and A0 pins) to ensure proper device selection. This comparison is in addition to the "Device Type" comparison. In addition to selecting an EEPROM, these 3 bits are also used to select a "page block" within the selected EEPROM. Each page block is 512Kbit (64 K Bytes) in size. If an EEPROM contains more than one page bock then the selection of a page block within the EEPROM is by using A2, A1 and A0 bits.
Read/Write Bit
Last bit of the Slave Address indicates if the intended access is Read or Write. If the bit is "1," then the access is Read, whereas if the bit is "0," then the access is Write.
Acknowledge
Acknowledge is an active LOW pulse on the SDA line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. The receiver provides an ACK pulse for every 8-bits of data received. This handshake mechanism is done as follows: After transmitting 8-bits of data, the transmitter releases the SDA line and waits for the ACK pulse. The addressed receiver, if present, drives the ACK pulse on the SDA line during the 9th clock and releases the SDA line back (to the transmitter). Refer Figure 3.
Slave Address
Slave Address is an 8-bit information consisting of a Device type field (4bits), Device/Page block selection field (3bits) and Read/ Write bit (1bit).
Array Address#1
This is an 8-bit information containing the most significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device.
Slave Address Format
Device Type Identifier Device/Page Block Selection
Array Address#0
This is an 8-bit information containing the least significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device.
1
0
1
0
A2
A1
A0
R/W
(LSB)
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Device Operation
The FM24C128 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the FM24C128 will be considered a slave in all applications.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
Write Protect (WP)
If tied to VCC, PROGRAM operations onto the entire memory will not be executed. READ operations are possible. If tied to VSS, normal operation is enabled, READ/WRITE over the entire memory is possible. This feature allows the user to assign the entire memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. This pin has an internal pull-down circuit. However, on systems where write protection is not required it is recommended that this pin is tied to VSS.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer Figure 1.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The FM24C128 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Refer Figure 2.
Stop Condition
All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the FM24C128 to place the device in the standby power mode. Refer Figure 2.
Device Selection Inputs A2, A1 and A0 (as appropriate)
These inputs collectively serve as "chip select" signal to an EEPROM when multiple EEPROMs are present on the same IIC bus. Hence these inputs should be connected to VCC or VSS in a unique manner to allow proper selection of an EEPROM amongst multiple EEPROMs. During a typical addressing sequence, every EEPROM on the IIC bus compares the configuration of these inputs to the respective 3 bit "Device/Page block selection" information (part of slave address) to determine a valid selection. For e.g. if the 3 bit "Device/Page block selection" is 1-0-1, then the EEPROM whose "Device Selection inputs" (A2, A1 and A0) are connected to VCC-VSS-VCC respectively, is selected.
FM24C128 Array Addressing
During Read/Write operations, addressing the EEPROM memory array involves in providing 2 address bytes, "Word Address 1" and "Word Address 0." However on FM24C128 only the 6 least significant bits (LSB) of "Word Address 1" byte are used in decoding the access location. The remaining 2 bits are not used and are recommended to be set to "0." All 8 bits of the "Word Address 0" byte are used in decoding the access location.
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Data Validity (Figure 1)
SCL
SDA
DATA STABLE DATA CHANGE
Start and Stop Definition (Figure 2)
SCL
SDA START CONDITION STOP CONDITION
Acknowledge Response from Receiver (Figure 3)
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER
1
8
9
tDH
DATA OUTPUT FROM RECEIVER
START CONDITION
tAA
ACKNOWLEDGE PULSE
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Operations
BYTE WRITE
For byte write operation, two bytes of address are required after the slave address. These two bytes select 1 out of the 16,384 locations in the memory. The master provides these two address bytes and for each address byte received, FM24C128 responds with an acknowledge pulse. Master then provides a byte of data to be written into the memory. Upon receipt of this data, FM24C128 responds with an acknowledge pulse. The master then terminates the transfer by generating a stop condition, at which time the FM24C128 begins the internal write cycle to the memory. While the internal write cycle is in progress the FM24C128 inputs are disabled, and the device will not respond to any requests from the master for the duration of tWR. Refer Figure 4 for the address, acknowledge and data transfer sequence.
Page Write is initiated in the same manner as the Byte Write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 63 more bytes. After the receipt of each byte, FM24C128 will respond with an acknowledge pulse, increment the internal address counter to the next address, and is ready to accept the next data. If the master should transmit more than 64 bytes prior to generating the STOP condition, the address counter will "roll over" and previously loaded data will be re-loaded. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. Refer Figure 5 for the address, acknowledge, and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host's write operation, the FM24C128 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the FM24C128 is still busy with the write operation, no ACK will be returned. If the FM24C128 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
PAGE WRITE
To minimize write cycle time, FM24C128 offers Page Write feature, which allows simultaneous programming of up to 64 contiguous bytes. To facilitate this feature, the memory array is organized in terms of "Pages". A Page consists of 64 contiguous byte locations starting at every 64-Byte address boundary (for example, starting at array address 0x0000, 0x0040, 0x0080 etc.). Page Write operation is confined to a single page. In other words a Page Write operation will not cross over to locations on the next page but will "roll over" to the beginning of the same page whenever end of page is reached and additional data bytes are a continued to be provided. A Page Write operation can be initiated to begin at any location within a page (starting address of the Page Write operation need not be the starting address of a Page).
Write Protection
Programming of the entire memory will not take place if the WP pin of the FM24C128 is connected to VCC. The FM24C128 will respond to slave and byte addresses; but if the memory accessed is write protected by the WP pin, the FM24C128 will not generate an acknowledge after the first byte of data has been received. Thus the program cycle will not be started when the stop condition is asserted.
Byte Write (Figure 4)
S T Bus Activity: A Master R T SDA Line Bus Activity: EEPROM
A C K A C K A C K A C K
SLAVE ADDRESS
WORD ADDRESS (1)
WORD ADDRESS (0)
DATA
S T O P
Page Write (Figure 5)
S T Bus Activity: A Master R T SDA Line Bus Activity SLAVE ADDRESS WORD ADDRESS (1) WORD ADDRESS (0) DATA n DATA n+63 S T O P
1010 A C K A C K A C K A C K
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Read Operations
Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read.
will not acknowledge the transfer but does generate the stop condition, and therefore the FM24C128 discontinues transmission. Refer Figure 7 for the address, acknowledge, and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The FM24C128 continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential with the data from address n followed by the data from n + 1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" to the beginning of the memory. FM24C128 continues to output data for each acknowledge received. Refer Figure 8 for the address, acknowledge, and data transfer sequence.
Current Address Read
Internally the FM24C128 contains an address counter that maintains the address of the last byte accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to "1," the FM24C128 issues an acknowledge and transmits the eight bit word. The master will not acknowledge the transfer but does generate a stop condition, and therefore the FM24C128 discontinues transmission. Refer Figure 6 for the sequence of address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to "1," the master must first perform a "dummy" write operation. The master issues the start condition, slave address with the R/W bit set to "0" and then the byte address. After the byte address acknowledge, the master immediately issues another start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the FM24C128 and then by the eight bit word. The master
Current Address Read (Figure 6)
Bus Activity: Master SDA Line Bus Activity: EEPROM S T A R T SLAVE ADDRESS 101 0 1 A C K NO A C K S T O P
DATA
Random Read (Figure 7)
S T A Bus Activity: R Master T SDA Line Bus Activity: EEPROM S T A R T S T O P
SLAVE ADDRESS
0 A C K
WORD ADDRESS (1)
WORD ADDRESS (0)
SLAVE ADDRESS
1
DATA
A C K
A C K
A C K
NO A C K
Sequential Read (Figure 8)
Bus Activity: Master SDA Line Bus Activity: EEPROM A C K
DATA n +1 DATA n +1 DATA n + 2 DATA n + x Slave Address
A C K
A C K
A C K
S T O P
NO A C K
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.019 MAX. 0.014 MIN.
0.325 MAX. 0.305 MIN.
0.050 BSC 2. 0.206 0.004 0.206 0.004 1. 0.008 0.0098 MAX. 0.0020 MIN.
LEADFRAME THICKNESS +0.0015 -0.0005
7 REF ALL SIDE.
0.032 0.002
0.80 MAX.
NOTE :
1. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED 0.006 INCH PER SIDE 2. DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.010 INCH PER SIDE. 3. THIS PART IS COMPLIANT WITH EIAJ SPECIFICATION ED-7402-1. 4. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC.(S)
0.030 MAX. 0.020 MIN. 0.208 0.004
2.
0 - 8
8-Pin Molded Small Outline Package (MW8) Package Number M08D
0.114 - 0.122 (2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ (0.65) Typ
0.246 - 0.256 (6.25 - 6.5)
0.123 - 0.128 (3.13 - 3.30)
1
4
Pin #1 IDENT
Land pattern recommendation
0.0433 Max (1.1) 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ.
See detail A
0.0035 - 0.0079
0.0075 - 0.0118 (0.19 - 0.30)
0-8
Gage plane
DETAIL A Typ. Scale: 40X
0.020 - 0.028 (0.50 - 0.70) Seating plane
0.0075 - 0.0098 (0.19 - 0.25)
Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Lead Molded Thin Shrink Small Outline Package (MT8) Package Number MTC08
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FM24C128 Rev. B.1
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FM24C128 - 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1 0.032 0.005 (0.813 0.127) RAD 0.250 - 0.005 (6.35 0.127) Pin #1 IDENT
8
7
8
+
7
6
5
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080) 0.040 Typ. (1.016)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524) 0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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